Sort circuit and method using multiple parallel sorts of the sorted items

ABSTRACT

In a sort circuit comprised of m sort stages, the sort stages perform respective sorts, in parallel, on each input word as it is received. In particular, in the j th  one of the stages, j=1,2, . . . m, a bit is associated with each different possible pattern of the values of the D j  highest-order digits in the input word, D 1  &gt;D 2  &gt; . . . D m . As each input word is received, the values of its D j  higher-order digits are examined and the associated bit is set. 
     During output processing, the j th  stage of the sort circuit receives from the (j+1) st  stage a D j+1  -digit pattern representing the D j+1  highest-order digits of a word or words previously input to the sort circuit. The D j+1  -digit pattern is used to identify the bits within the j th  stage associated with the D j  -digit patterns whose D j+1  highest-order digits match the input pattern. The bits thus identified are processed within the j th  stage using priority logic circuitry so as to provide the D j  -digit patterns associated with the ones of the identified bits which are set. These D j  -digit patterns are provided to the (j-1) st  stage as its input digit pattern or, in the case of j=1, to the utilizing system. When the j th  stage has processed all of the bits identified in response to a particular D j+1  -digit pattern, it requests a new pattern from the (j+1) st  stage.

BACKGROUND OF THE INVENTION

The present invention relates to electronic sorting.

As the state of VLSI technology has continued to provide increasedcircuit densities, it has become practical to migrate into hardware manydata processing functions that have traditionally been implemented insoftware. Multiplication, array processing, and fast Fourier transformprocessing are but several examples. In this vein, much interest hasarisen in the past few years in the hardware realization of the sortingfunction, i.e., the rearrangement of a plurality of multi-digit inputwords or values in accordance with some predetermined criterion, such asnumerical order. Indeed, hardware implementation of many of the standardsorting techniques have been proposed. A number of these arrangementsare described, for example, in C. D. Thompson, "The VLSI Complexity ofSorting," Memorandum No. UCB/ERL M82/5, Electronics Research Laboratory,College of Engineering, University of California, Berkeley, Feb. 14,1982. A disadvantage of most of the known sorting techniques is that inaddition to the time required for input/output (I/O), a substantialamount of processing time is required to perform the sort itself. Thearrangement described by Thompson, for example, require anywhere from Nto (N lg³ N) processing cycles to perform the sort, where N is thenumber of values being sorted. At least one arrangement is known whichmay require very little, if any, sort processing time. See, for example,U.S. Pat. No. 4,030,077 issued June 14, 1977 to J. K. Florence et al.That arrangement, however, requires a substantial amount of circuitry todo the job.

SUMMARY OF THE INVENTION

The present invention is directed to a sort circuit which overcomes manyof the disadvantages of the prior art. In preferred embodiments of theinvention, a plurality of m stages within the sort circuit performrespective sorts, in parallel, on each multi-digit input word as it isreceived. In particular, in the j^(th) one of the stages, j=1,2 . . . m,a bit (or other indicator) is associated with each different possiblepattern of the values of the D_(j) highest-order digits in the inputword, D₁ >D₂ > . . . >D_(m). As each input word is received, the valuesof its D_(j) highest-order digits are examined and the associated bit isset. Since there are m sort stages, then m bits are set as each word isinput.

Very shortly after the last input word has been applied to the sortcircuit, it is ready to begin, in response to the bits which were set,to put out the received words in sorted order. In particular, for j=1,2. . . (m-1), the j^(th) stage of the sort circuit receives from the(j+1)^(st) stage a D_(j+1) -digit pattern representing the D_(j+1)highest-order digits of a word or words previously input to the sortcircuit. The D_(j+1) -digit pattern is used to identify the bits withinthe j^(th) stage associated with those D_(j) -digit patterns whoseD_(j+1) highest-order digits match the D_(j+1) -digit pattern. The bitsthus identified are processed within the j^(th) stage so as to providethe D_(j) -digit patterns associated with the ones of the identifiedbits which are set. These D_(j) -digit patterns are provided to the(j-1)^(st) stage or, in the case of j=1, to the utilizing system. Whenthe j^(th) stage has processed all of the bits identified in response toa particular D_(j+1) -digit pattern, it requests a new pattern from the(j+1)^(st) stage. Illustratively, the m^(th) sort stage does not receiveany input patterns. Rather, it simply responds to each request from the(m-1)^(st) stage to provide thereto a respective D_(m) -digit patternwhose associated bit in the m^(th) stage is set.

The process repeats until all of the words have been output.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1-2, when arranged as shown in FIG. 3, comprise a block diagram ofa sort circuit which performs the sorting technique of the presentinvention;

FIG. 4 is a block diagram of one of the sort stages of the sort circuitof FIGS. 1-2;

FIG. 5 is a block diagram of an auxiliary circuit which can be used inconjunction of the sort circuit of FIGS. 1-2 in order to keep track ofduplicate values in the input word stream; and

FIG. 6 is a block diagram of an auxiliary circuit which can be used inconjunction with the sort circuit of FIGS. 1-2 to sort pairs ofcoordinates in accordance with one of the coordinate values.

DETAILED DESCRIPTION

FIGS. 1-2, when arranged as shown in FIG. 3, depict a sort circuit whichperforms the sorting technique of the present invention. In particular,the sorting is performed by a plurality of m sort stages which operatein parallel on each input word to be sorted as the word is received. Inthe j^(th) sort stage, S_(j), an indicator in the form of a memory bitis associated with each different possible pattern of the values of theD_(j) highest-order binary digits in the input word, D₁ >D₂ > . . .>D_(m). Illustratively, the words being sorted are binary words. Thusstage S_(j) includes 2^(D).sbsp.j memory bits each associated with arespective one of the 2^(D).sbsp.j different possible D_(j) -digitpatterns.

In the present illustrative embodiment, more particularly, the word tobe sorted are of 9-bit length. There are three sort stages S₁, S₂ andS₃. In addition, D₁ =9, D₂ =6, and D₃ =3. Thus, as shown in the drawing,sort stage S₁ includes a memory 10 comprising 2⁹ =512 memory bits, sortstage S₂ includes a memory 20 comprising 2⁶ =64 memory bits and sortstage S₃ includes a memory 30 comprising 2³ =8 memory bits. To the leftof each memory bit in stage S_(j) is shown the D_(j) -digit pattern withwhich it is associated.

As will become apparent as this description continues, the sort circuitof FIGS. 1-2 does not keep track of duplicate input word values. Thatis, a value is provided only once in the sorted word output stream, nomatter how many times it appeared in the input stream. For manyapplications this is not a disadvantage and, indeed, is desirable. If,on the other hand, it is desired to keep track of duplicate values,further circuitry can be combined with that of FIGS. 1-2 to perform thisfunction. Illustrative such circuitry is shown in FIG. 5 and isdescribed hereinbelow.

Input processing is performed by the sort circuit of FIGS. 1-2 asfollows:

A system requiring the services of the sort circuit provides the inputwords to be sorted on the three leads 45a-c, each of which carries threedigits of the input words. The D₃ =3 highest-order digits, on lead 45a,are applied to sort stage S₃ ; the D₂ =6 highest-order digits, on leads45a-b, are applied to sort stage S₂ ; and the D₁ =9 highest-orderdigits, on leads 45a-c, i.e., the entire word, are applied to sort stageS₁. As the system provides each input word on leads 45a-c, it pulses"input new word" lead 41, which extends to each sort stage. Theutilizing system, in addition, holds load/unload lead 42 high, therebyindicating to each sort stage that it is to operate in its input, or"load," mode.

Each sort stage responds to the above-described combination of inputs bysetting a single bit to "1" in its respective memory, that bit being, insort stage S_(j), the bit associated with the values of the D_(j)highest-order digits of the input word. (Throughout this description, abit is said to be "set" whenever the mechanism for setting its value to"1" is invoked, independent of the then current value of the bit. Thus abit can be "set" any number of times, even though it is only the first"set" operation that changes its value from "0" to "1".)

By way of example, a number of bits in memories 10, 20 and 30 are shownas set, those bits having been set upon input processing of thefollowing words in the order given:

word A--100101000

word B--000000110

word C--000010111

word D--100101000

word E--100101101

word F--000000100

word G--111111001

When word A was received, the bits that were set were (a) the bit inmemory 10 associated with the pattern which matches word A's D₁ =9highest-order digit values, i.e., the entire word, (b) the bit in memory20 associated with the pattern which matches word A's D₂ =6highest-order digit values, i.e., 100101, and (c) the bit in memory 30associated with the pattern which matches word A's D₃ =3 highest-orderdigit values, i.e., 100. Similarly when word B was received, the memorybits that were set were the bits associated with the digit patterns000000110 (memory 10), 000000 (memory 20) and 000 (memory 30).

When word C was received, however, bits only in memories 10 and 20changed values when they were set because the associated bit in memory30, i.e., the bit associated with the pattern of its D₃ =3 highest-orderbits, 000, was previously set when word B was input. Word D, being aduplicate of word A, caused no new bit values to be changed, and soforth.

Once the last word has been input to the sort circuit, output processingand output of the words in sorted order can begin at a time no more thanm read cycle times after the last word was input, m being, again, thenumber of stages in the sort circuit. We will first describe the outputprocessing with reference to the specific embodiment of FIGS. 1-2 andthen restate the output processing mechanism in general terms.

In particular, the system utilizing the services of the sort circuitinitiates the output processing by switching load/unload lead 42, to thelow state. In response, sort stage S₃ processes the bits in memory 30 soas to reconstruct the digit pattern of the D₃ =3 highest-order digits ofthe first word to be output. (As will be described in further detailhereinbelow, priority encoder circuitry is illustratively used in eachsort stage to perform this processing in such a way that there is verylittle delay associated therewith.) Assuming that the sorted words areto be output in ascending order, the digit pattern reconstructed by sortstage S₃ is 000 since that is the lowest-valued pattern whose associatedbit is set. The reconstructed digit pattern is applied via leads 35a tostate S₂.

An unload startup circuit 51, which is illustratively comprised on twoD-type flip flops connected in series, provides a pulse to sort stage S₂on lead 52 at a predetermined time after the transition on lead 42. Sortstate S₂ responds to this pulse by reading in the three-digit pattern onleads 35a and then pulsing "new pattern request" lead 38. The latteraction causes stage S₃ to provide a second three-digit pattern on leads35a--in this case the pattern 100 since that is the nextlowest-valuedpattern whose associated bit is set in memory 30. A new three-digitpattern is thus ready to be read in by stage S₂ when it is needed.

Meanwhile, stage S₂ processes the bits associated with the just-read-inpattern 000. The bits identified by that pattern, as denoted in thedrawing by the bracketed "000", are the bits associated with the eightpatterns 000000, 000001, . . . , 000111. (Note that it is guaranteedthat at least one of those bits will have been set; if not, the bit inmemory 30 associated with the pattern 000 would not have been set.)Stage S₂, upon processing the bits stored in memory 20 identified by thepattern 000, determines that the lowest-valued six-digit pattern whoseassociated ones of those identified bits is set is the pattern 000000.That pattern is provided to the next-lower-order stage, i.e., stage S₁on leads 25a-b, each of which carries a respective three of the sixdigits of the pattern.

Circuit 51 provides a pulse on lead 53 at a time which is sufficientlysubsequent to the pulse on lead 52 to allow stage S₂ to provide thesix-digit pattern on leads 25a-b as just described. Sort stage S₁responds to the pulse on lead 53 by reading in the pattern on leads25a-b and then pulsing "new pattern request" lead 28. The latter actioncauses stage S₂ to provide, on leads 25a-b, a second six-digitpattern--in this case the pattern 000010 since that is thenext-lowest-valued pattern whose associated bit is set in memory 20. Anew pattern is thus ready to be read in by stage S₁ when it is needed.

Meanwhile, stage S₁ processes the bits associated with the patternswhose highest-order digits match the pattern 000000. The bits thusidentified in stage S₁ are, of course, the bits associated with theeight patterns 00000001, 000000010 . . . 000000111. (Note that it isguaranteed that at least one of those bits will have been set; if not,the bit in memory 20 associated with the digit pattern 000000 would nothave been set.)

Stage S₃, upon processing the bits stored in memory 10 identified by thepattern 000000, determines that the lowest-valued nine-digit patternwhose associated bit is set is the pattern 000000100. That pattern is,in fact, the smallest of the seven input word values (word F) and it isprovided to the utilizing system by stage S₁ on sort circuit outputleads 15a-c when the system requests same by pulsing "output new value"lead 18. It will thus be appreciated that, as previously noted, thefirst word is ready to be put out no more than m=3 read cycle timesafter the last word was input.

Stage S₁ further responds to the pulse on lead 18 by again processingthe bits identified by the pattern 000000 to provide the next-in-order,not-yet-output word whose associated one of those identified bits isset--in this case, the word 000000110 (word B). That word is thus readyto be output on leads 15a-c when lead 18 is again pulsed.

At this point, all of the set bits identified by the input digits 000000have been processed. As a result, when lead 18 is in fact pulsed again,stage S₁, in response, not only provides the second output word on leads15a-c, as just described, but also (a) reads in the new six-digitpattern 000010 already waiting on leads 25a-b and, thereafter (b) pulses"new pattern request" lead 28. Stage S₂ responds to the pulse on lead 28by providing a new six-digit pattern on leads 25a-b so that it will beready to be read in by stage S₁ when needed. For the moment, however, wecontinue to focus attention on stage S₁.

In particular, stage S₁ now process the bits associated with thepatterns whose first six digits match the new pattern 000010. There isone such bit--the one associated with the pattern 000010111--and, asbefore, stage S₁ provides that pattern on leads 15a-c as the next sortcircuit output word when lead 18 is pulsed.

At this point, all of the set bits in memory 10 identified by thepattern 000010 have been processed. Thus when lead 18 is in fact pulsedagain, stage S₁ again (a) reads in the new six-digit pattern 100101 onleads 25a-b, and (b) pulses lead 28, and so forth, until all of thewords have been put out.

Meanwhile, of course, processing of the bits stored in stages S₂ and S₃has also been going on in order to generate the patterns to be appliedto stages S₁ and S₂, respectively. In particular, stage S₂ (S₃) operatesto provide new six-digit (three-digit) pattern on leads 25a-b (15a) inmuch the same way as stage S₃ operates to provide output words on leads15a-c. For example, stage S₂ responds to each pulse on lead 28 byprocessing the bits in memory 20 identified by the three-digit patternmost recently read in from leads 35a, to provide on leads 25a-b thenext-in-order, not-yet-output six-digit pattern whose associated one ofthose bits is set. Whenever all of the set bits identified by thepattern on leads 35a have been proposed, stage S₂ both reads in the newthree-digit pattern already waiting on leads 35a and thereafter pulses"new input pattern" request lead 38 so that stage S₃ will make ready anew three-digit input pattern.

Similarly, stage S₃ responds to each pulse on lead 38 by processing thebits in memory 30 and providing the next-in-order, not-yet-outputthree-digit pattern whose associated bit is set.

Once all of the set bits in memory 30 have been processed, stage S₃pulses "empty" lead 48, which extends to unload completion detector 58.Leads 38 and 28 also extend to detector 58 and when all three of leads48, 38 and 28 have been pulsed in that order, detector 58 pulses "unloadcomplete" lead 59, thereby indicating that all the words have beenoutput. (Although not shown in the drawing, detector 58 illustrativelycomprises two D-type flip flops, with leads 48, 38 and 28 beingrespectively connected to the D input of the first flip flop; the clockinput of the first flip flop; and the clock input of the second flipflop. In addition, the output of the first flip flop is connected to theD input of the second flip flop and the output of the second flip flopis connected to lead 59.)

Having described the output, or "unloading" operation of theillustrative embodiment, we can now characterize that operation in ageneral way as follows:

At any point in the output processing, once initiated, sort stage S_(j),for j=1,2, . . . (m-1), has received a D_(j+1) -digit pattern, thelatter representing the D_(j+1) highest-order digits of a word or wordthat was input to the sort circuit during input processing. The D_(j+1)-digit pattern received by stage S_(j) is used thereby to identify thebits within that stage associated with the D_(j) -digit patterns whoseD_(j+1) highest-order digits match the input digit pattern. The bitsthus identified are processed within stage S_(j), in response tosuccessive requests from stage S_(j-1), so as to provide the D_(j)-digit patterns associated with the ones of the identified bits whichare set. These D_(j) -digit patterns are provided to the (j-1)^(st)stage or, in the case of j=1, to the utilizing system. When stage S_(j)has processed all of the bits identified in response to the currentdigit pattern, it requests a new pattern from stage S.sub. j+1. StageS_(m) does not receive any input patterns. Rather, it simply responds toeach request from stage S_(m-1) to provide thereto a respective D_(m)-digit pattern whose associated bit in stage S_(m) is set.

FIG. 4 is a block diagram of sort stage S₂. Sort stages S₁ and S₃ arevery similar and will not be described in detail. The differences amongthe several sort stages are, however, discussed hereinafter.

As indicated in FIG. 4, load/unload lead 42 extends to an addressmultiplexer 101. During input processing by the sort circuit,load/unload lead 42 is low. This causes multiplexer 101 to pass thethree highest-order digits of the input words on leads 45 onto leads 102to serve as addresses for 64-bit memory 20.

Each three-digit address on leads 102 identifies an 8-bit word in memory20, namely the eight bits associated with the eight six-digit patternswhose three highest-order digits are the same as the three-digitaddress. Memory 20 responds by providing that 8-bit word on its outputleads 111.

As will now be described, the particular bit on leads 111 associatedwith the six highest-order digits of the input word is now set to "1"and the 8-bit word, thus modified, is written back into memory 20.

Load/unload lead 42 extends not only to address multiplexer 101, butalso a second, control multiplexer 134. The current, low state of thatlead causes multiplexer 134 to pass the pulses on lead 41 onto lead 135.The latter extends to the clock inputs of D-type flip-flops 122, whileeach one of leads 111 extends to the D input of a respective one ofthose flip flops. Thus as each new input word appears on leads 45, thebits on leads 111 are clocked into respective ones of flip flops 122,with one important exception as will now be explained.

The three next-lowest-order digits of the input words, i.e., its fourththrough six highest-order digits are applied to 3-to-8 decoder 116.Decoder 116 is a standard circuit which provides a "1" on a particularone of its eight output leads 117 depending on which one of the eightpossible three-bit combinations is provided to it. Each one of leads 115extends to the set input of a respective one of flip-flops 122.Providing a "1" at the set input of a D-type flip-flop immediatelyswitches its Q output to "1" independent of any value clocked in fromits D input. The Q outputs of flip-flops 122 extend to the inputs ofmemory 20 and the pulse on lead 135 extends not only to the clock inputsof flip-flops 122, but also to the write input of memory 20. The overallresult, as stated at the outset, is that the bit in memory 20 associatedwith the six highest-order digits of the input word is set to "1" injust the manner described above in conjunction with the diagram of FIGS.1-2. The process repeats for each input word.

When unload processing is initiated, the pulse provided by start-upcircuit 51 on lead 52, passes onto lead 38 via OR gate 131. Lead 38extends to the enable input of a latch 127 and, at this point, sortstage S₃ has already provided the first three-digit pattern on leads 35.Thus, the pulse on lead 38 causes that pattern to be loaded into latch127. As already described in conjunction with FIGS. 1-2, the pulse onlead 38 also passes back up to sort stage S₃, thereby requesting thatthe next three-digit pattern be provided on leads 35.

Since load/unload lead 42 is now high, multiplexer 101 provides thecontents of latch 127, rather than digits on leads 45, as the addressfor memory 20. This identifies to memory 20 the bits associated with theeight six-digit patterns whose three highest-order digits match theinput pattern. As before, those bits are provided by memory 20 on itsoutput leads 111.

Leads 111 extend not only to flip-flops 111 as previously described, butalso to 8-to-3 priority encoder 139. This is a standard type of circuitwhich provides to sort stage S₁ on leads 25b the three lowerorder digitsof the lowest-valued six-digit pattern whose associated one of the bitson leads 111 is set. At the same time, the three-digit pattern stored inlatch 127, comprising the three highest-order digits of the six-digitpattern in question, is provided to stage S₁ on leads 25a.

Since load/unload lead 42 is now high, multiplexer 134 takes its inputfrom new pattern request lead 28, thereby causing flip-flops 122 to beclocked, and memory 20 to be written, whenever lead 28 is pulsed. As inthe input processing case, this causes the bits on leads 111 to bewritten back into the memory with one exception. The exception is thatis is necessary to change the bit associated with the pattern on leads25a-b from "1" to "0" so that priority encoder 139 can provide the nextthree-digit pattern on leads 25b. To this end, leads 25b extend to3-to-8 decoder 137 which responds to the current pattern on leads 25b byproviding a "1" on a particular one of its output leads 138 associatedwith that pattern. Each one of leads 138 extends to the clear input of arespective one of flip flops 122, thereby causing the flip-flopassociated with the one of leads 111 whose "1" was just encoded bypriority encoder 139 to be changed to "0" and thereby changing the bitin question from a "1" to a "0" in memory 20.

The output processing proceeds in this manner until the six-digitpattern associated with each set one of the bits identified by the inputpattern in latch 127 has been provided on leads 25b. It is premature,however, for stage S₂ to latch in the new pattern waiting on lead 35because that pattern must continue to be provided to stage S₁ on leads25a until such time as that stage has read in the pattern which includesthe new three digits now waiting on leads 25b.

Once stage S₁ has read in that pattern, however, it pulses lead 28. Theresulting "1" on that lead is inverted to a "0" by inverter 132, theoutput of which is applied to one input of NOR gate 104. The remaininginputs of NOR gate 104 are taken from the Q outputs of flip flops 122,which are all "0" at this time. Accordingly, the output of NOR gate 104goes high, thereby pulsing lead 38 via OR gate 131. This causes thethree-digit pattern waiting on leads 35a to be latched into latch 127and a new pattern to be thereafter supplied on those leads by sort stageS₃. The process repeats until all of the patterns have been output.

As previously noted, sort stages S₁ and S₃ are very similar to sortstage S₂. However, stage S₃ does not include circuitry corresponding tolatch 35 or multiplexer 101. Indeed, since memory 30 stores but a single8-bit word, no addresses need be applied thereto. The differencesbetween stage S₂ and stage S₁ are that the latter's latch receives, andis adapted to hold, six-rather than three-digit patterns, i.e., thepatterns appearing on leads 25a-b. Similarly, its address multiplexerreceives, and is adapted to multiplex, six-rather than three-digitpatterns. Moreover, in stage S₁ "output new value" lead 18 substitutesfor "new pattern request" lead 28 of stage S₂.

As noted above, the sort circuit of FIGS. 1-2 does not keep track ofduplicate values. If desired, however, duplicate values can be kepttrack of using the auxiliary circuit shown in FIG. 5 in conjunction withthe sort circuit of FIGS. 1-2.

In particular, the auxiliary circuit of FIG. 5, like the sort circuititself, receives the 9-digit input words on leads 45a-c, which are shownin FIG. 5 as being bundled into a cable 45. The auxiliary circuit alsoreceives the 8-bit output words of memory 10 (FIGS. 1-2) on leads 141.The latter leads, although not shown explicitly elsewhere in thedrawing, correspond generally to output leads 111 of memory 20. Leads141 extend to 8-to-1 data selector 143, which responds to the 3-digitpattern on leads 45c to provide on its output lead 144 the value of thebit associated with the current input word. Lead 144, in turn, extendsto one input of each one of eight AND gates 153.

The first time a particular input value occurs during input processing,lead 144 carries a "0" since the associated bit in memory 10 is "0". Theoutputs of AND gates 153 are thus all "0", thereby providing the binaryword 00000000 to increment circuit 156. The function of the latter is toincrement by unity the word provided to it, and thus at this time itprovides the binary word 00000001 via a cable 157 to the data input ofan extension memory 151.

Memory 151 stores an 8-bit count associated with each input word valueto indicate how many times the value in question has occurred in theinput word stream. At this time, the address input of memory 151 isreceiving the input word on cable 45 via a multiplexer 148. Thus when"input new word" lead 41--which extends to the write input of memory151--is pulsed, the binary count 00000001 is stored in a location withinmemory 151 associated with the current input word value, therebyindicating that that value has thus far occurred once.

Each one of AND gates 153 receives its second input from a respectiveone of the eight output leads 152 of memory 151. Since lead 144 carriesa "1" upon the second and each subsequent occurrence of a particularinput value, AND gates 153 are enabled upon any such occurrence to passthe current count associated with that input value to increment circuit156. That count is thus again incremented by unity and then rewritteninto the memory.

The auxiliary circuit of FIG. 5 also receives leads 15a-c, which areshown in FIG. 5 as being bundled into a cable 15. During outputprocessing, multiplexer 148 provides the 9-digit sorted words from cable15 to the address input of memory 151. Thus as each sorted word inoutput on cable 15, the count associated therewith is provided on leads152, and thence onto a cable 16.

Since memory 151 stores 8-bit words, the auxiliary circuit is capable ofkeeping track of 2⁸ =256 duplicates of each input value. If more than256 duplicates are possible in a particular application, the extensionmemory can be enlarged accordingly.

Another auxiliary circuit that can be used in conjunction with the sortcircuit of FIGS. 1-2 is shown in FIG. 6. This circuit is useful inreal-time graphics display applications, for example, where it isdesired to sort sets of (x,z) coordinates in accordance with thex-value. If more than one coordinate has the same x-value, then it isdesired to provide in the sorted-by-x-value-coordinate output stream theone of those (x,z) coordinates having the smallest z-value.

The circuit of FIG. 6 is similar in many respects to that of FIG. 5 andthe corresponding components bear the same reference numerals.

During input processing, the x-values appear on cable 45 and theaccompanying z-values--referred to as "qualifiers"--appear on leads19a-c of a cable 19. The x-values are sorted by the sort circuit ofFIGS. 1-2, as previously described, and within the auxiliary circuit ofFIG. 6, as in the auxiliary circuit of FIG. 5, lead 144 carries a "0"the first time that a particular value occurs. That "0" is inverted atthe inhibit input of OR gate 146, thereby providing a "1" to one inputof AND gate 147. The other input of AND gate 147 is taken from "inputnew value" lead 41, while the output thereof extends to the write inputof extension memory 151. The input to memory 151 comprises the z-valueson cable 19 while its addresses are taken from cable 45 via multiplexer148. The overall result, then, is that the first time a particularx-value occurs, the accompanying z-value is automatically written intomemory 151.

At any subsequent time that that particular x-value occurs, theaccompanying z-value overwrites the z-value previously stored in thememory only if the new z-value is smaller than the old one. Inparticular, since lead 144 carries a "1" at the second and anysubsequent time that a particular x-value occurs, the output of OR gate144 is "1", thereby causing the new z-value to be written in the memory,only if output lead 163 of comparison circuit 162 carries a "1". Andthat, in turn, will occur only if in fact the new z-value is smallerthan that already stored.

During output processing, multiplexer 148 provides the addresses formemory 151 from cable 15 so that each z-value stored in memory 151appears on the memory output cable 154 concomitant with the appearanceof the corresponding sorted x-values on cable 15.

The foregoing merely illustrates the principles of the invention. Forexample, the invention can be used to sort values whose base is otherthan 2. Moreover, there are no constraints on how many sort stages areused to sort words of any given length nor are there any constraints,apart from what is explicitly stated above, as to how the D_(j) 's arechosen. In general, however, it is most efficient to select theseparameters such that the quantity [D_(j+1) -D_(j) ] is the same for allj.

It will thus be appreciated that numerous arrangements may be devised bythose skilled in the art which, although not explicitly shown ordescribed herein, embody the principles of the invention.

I claim:
 1. Apparatus for sorting a plurality of multi-digit words, saidapparatus comprisinga plurality of indicators, means responsive to eachof said multi-digit words for setting m selected ones of saidindicators, m≧2, the j^(th) of said m indicators, j=1,2, . . . m, beingselected as a function of the values of the first through D_(j) ^(th)highest-order digits of said each multi-digit word, D₁ >D₂ > . . .>D_(m), and output means responsive to said set ones of said indicatorsfor putting out said multi-digit words in a sorted order.
 2. Apparatusfor sorting a plurality of multi-digit words, said apparatus comprisingmsort stages, m≧2, the j^(th) of said stages, j=1,2, . . . m, including aplurality of indicators each corresponding to a different possiblepattern of the values of the first through D_(j) ^(th) highest-orderdigits of said multi-digit words, D₁ >D₂ > . . . >D_(m), meansresponsive to each of said multi-digit words for setting in said j^(th)sort stage the indicator corresponding to the values of the firstthrough D_(j) ^(th) highest-order digits of said each of saidmulti-digit words, and output means responsive to the set ones of saidindicators for putting out said multi-digit words in a sorted order. 3.The apparatus of claim 2 wherein said output means includes means insaid j^(th) stage for at least one value of j, the last-mentioned meanscomprisingmeans responsive to a D_(j+1) -digit pattern provided to saidj^(th) stage from the (j+1)^(st) stage for identifying the indicatorswithin said j^(th) stage corresponding to D_(j) -digit patterns whichhave said D_(j+1) -digit pattern as their first through D_(j+1) ^(st)highest-order digits, and means at least responsive to the set ones ofthe identified indicators for providing to the (j-1)^(st) stage theparticular D_(j) -digit patterns associated with said set ones of theidentified indicators.
 4. The apparatus of claim 3 wherein saidproviding means includes priority encoder means and means forrepetitively (a) applying said identified indicators to said priorityencoder means to provide at least a portion of an individual one of saidparticular D_(j) -digit patterns for the (j-1)^(st) sort stage and (b)clearing the individual one of said set ones of said identifiedindicators associated with said individual one of said D_(j) -digitpatterns.
 5. The apparatus of claims 3 or 4 wherein said j^(th) stageincludes means operative after all of said particular D_(j) -digitpatterns have been provided to said (j-1)^(st) stage for requesting thata new D_(j+1) -digit pattern be provided to said j^(th) stage from said(j+1)^(st) stage.
 6. A method for sorting a plurality of multi-digitwords, said method comprising the steps ofsetting m selected ones of aplurality of indicators in response to each of at least ones of saidmulti-digit words, m≧2, the j^(th) of said m indicators, j=1,2, . . . m,being set as a function of the values of the first through D_(j) ^(th)highest-order digits of said each of said multi-digit words, D₁ >D₂ > .. . >D_(m), and putting out said multi-digit words in a sorted order inresponse to said set ones of said indicators.
 7. A method for sorting aplurality of multi-digit words, said method being adapted for use inconjunction with m pluralities of indicators, m≧2, the indicators in thej^(th) of said pluralities, j=1,2, . . . m, each corresponding to adifferent possible pattern of the values of the first through D_(j)^(th) highest-order digits of said multi-digit words, D₁ >D₂ > . . .>D_(m), said method comprising the steps ofsetting in response to eachof said multi-digit words the indicator in said j^(th) of saidpluralities corresponding to the values of the first through D_(j) ^(th)highest-order digits of said each of said multi-digit words, and puttingout said multi-digit words in a sorted order in response to the set onesof said indicators.